1. Field of the Invention
The present invention relates a data descrambling device of a PCI (Peripheral Component Interconnect) Express device, and more particularly to a data descrambling device capable of preventing a high bit error rate of a symbol disorder lane.
2. Description of the Prior Art
In following the development of technology, the requirements of bandwidth and speed for interconnected interface in personal computers and peripherals are continuing to increase. As this phenomenon continues it also causes the workload for a PCI bus to increase, hence the third generation input/output (3GIO) interface is being introduced. PCI Express bus can provide a greater bandwidth requirement. As known to those skilled in the art, the technology of PCI Express provides a faster operating clock and more lanes as means for upgrading its efficiency, therefore the first generation PCI Express technology can provide 2.5 GB (Giga Bytes) per second of raw bandwidth in each direction of each lane, hence greatly improving on the efficiency of the computer system. This improvement is especially obvious in the mapping processing.
Therefore, as long as a lane of a PCI Express can maintain a low bit error rate (BER), then the PCI Express can provide a high transmission service to the related devices. However, in actual operation, it is not guaranteed that the lane of the PCI Express can be maintained operating at an ideal (low) BER, and the higher the BER the easier it is to cause disorder to a symbol received at a receiving end which can affect the efficiency to reduce significantly.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 illustrate a diagram of a transmission end 100 and a receiving end 200 of a conventional PCI Express. The transmission end 100 includes a data scrambling circuit 102, an 8B10B decoder 104, and a transmitter 106. In FIG. 2 corresponding to FIG. 1, the PCI Express receiving end 200 includes a data scrambling circuit 202, an 8B10B decoder 204, an offset cancellation circuit 206, an elastic buffer 208, and a receiving device 210.
The physical layer of the PCI Express defines functions like coding/decoding of the 8B10B, scramble/descramble of data, and offset removal. The coding/decoding of the 8B10B can ensure that the receiving end 200 can receive a correct symbol; and the scramble/descramble of data can eliminate disturbance and electric magnetic effect in the lane. Furthermore, as operating clocks of the transmission end 100 and the receiving end 200 are different, therefore if the operating clock of the transmission end 100 is faster than the operating clock of the receiving end 200, then the transmission rate of output data-flow of the transmission end 100 will be faster than the receiving rate of retrieval data-flow of the receiving end 200, which will cause data to overflow. On the contrary, if the operating clock of the transmission end 100 is slower than the operating clock of the receiving end 200, then the transmission rate of the output data-flow of the transmission end 100 will be slower than the receiving rate of the retrieval data-flow of the receiving end 200, which will cause data to underflow. Therefore in order to solve the problem of different operating clocks of the transmission end 100 and the receiving end 200, the elastic buffer 208 is installed within the receiving end 200 which has a plurality of elastic buffers for regulating the data in the lane transmitted via the transmission end 100.
According to the PCI Express standards, the transmission end 100 will output an ordered set to the elastic buffer to balance the different operating clocks of the transmission end 100 and the receiving end 200. For example, each ordered set outputted by the transmission end 100 has a COM (COMMA) symbol and three SKP (SKIP) symbols. Therefore when an elastic buffer in the receiving end 200 receives a plurality of ordered sets, if the operating clock of the transmission end 100 is faster than the operating clock of the receiving end 200, the elastic buffer can achieve the objective of reducing the data transmission rate of the transmission end 100 via the reduced SKP symbols in the ordered set. Alternatively, if the operating clock of the transmission end 100 is slower than the operating clock of the receiving end 200, the elastic buffer can achieve the objective of upgrading the data transmission rate of the transmission end 100 via the increased SKP symbols in the ordered set. As a result, the above-mentioned problem can be avoided.
The PCI Express standards define five types of ordered sets. To reduce power consumption, when there is no packet in the lane of the PCI Express, the transmission end of the PCI Express will transmit an electrical idle set ordered to the receiving end. The electrical idle ordered set is formed by a COM symbol followed by three logic idle symbols where raw data of the logic idle symbol (before data scramble) is 0 byte (corresponding to the decoding of the 8B10B). Therefore if the decoding of the 8B10B of the receiving end of the PCI Express is accurate and the data descramble is error-free, then the receiving end can receive the raw 0 byte data. However, the BER of the lane of the actual PCI Express chipset and apparatus may not be lower than 10−12. When the BER of the lane exceeds 10−12, the logic idle symbol will be incorrectly decoded (i.e., a framing error will be obtained), more importantly, the logic idle symbol may be treated as a packet framing symbol or an ordered set as a result of the inaccurate data after descrambling. If the logic idle symbol is processed as a packet framing symbol, then the receiving end will report to an upper layer (e.g., such as a media access control layer) and execute a related action. Hence work is carried out during the system idle (as there is no actual packet framing symbol to be processed). Furthermore, if the logic idle symbol is processed as a set ordered, the connection of the physical layer of the PCI Express will be easily cut off. Therefore, the system efficiency will be greatly reduced when the BER of the lane of the PCI Express is too high.